The present invention generally relates to integrated circuits, and more specifically, to generating a functional logic cone signature for circuit analysis.
Integrated circuits generally include a large number of circuit components, such that the design of such circuits may be very large and complicated. On occasion, one or more components of an integrated circuit may experience failures and it is generally desirable to identify the source of such failures so that the circuit may be repaired or redesigned. Current approaches for attempting to detect systemic failures among circuit designs include core stacking and name masking, which rely on patterns in observation latch names.